IDT71T75802S100PFI8

IDT71T75802S100PFI8 Features

(3.2 ns Clock-to-Data Access)cyclesneed to control OEsignal registers for fully pipelined applicationsflatpack (TQFP), 119 ball grid array (BGA)for selected speeds

IDT71T75802S100PFI8 Description

The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit (18 Mega-bit) synchronous SRAMs. They are designed to eliminate dead buscycles when turning the bus around between reads and writes, or writesand reads. Thus, they have been given the name ZBTTM, or Zero BusTurnaround.Address and control signals are applied to the SRAM during one clockcycle, and two cycles later the associated data cycle occurs, be it read orwrite.The IDT71T75602/802 contain data I/O, address and control signalregisters. Output enable is the only asynchronous signal and can be usedto disable the outputs at any given time.A Clock Enable CEN pin allows operation of the IDT71T75602/802to be suspended as long as necessary. All synchronous inputs areignored when (CEN) is high and the internal device registers will hold theirprevious values.There are three chip enable pins (CE1, CE2, CE2) that allow the userto deselect the device when desired. If any one of these three is notasserted when ADV/LD is low, no new memory operation can be initiated.However, any pending data transfers (reads or writes) will becompleted. The data bus will tri-state two cycles after the chip is deselectedor a write is initiated.The IDT71T75602/802 have an on-chip burst counter. In the burstmode, the IDT71T75602/802 can provide four cycles of data for a singleaddress presented to the SRAM. The order of the burst sequence isdefined by the LBO input pin. The LBO pin selects between linear andinterleaved burst sequence. The ADV/LD signal is used to load a newexternal address (ADV/LD = LOW) or increment the internal burstcounter (ADV/LD = HIGH).The IDT71T75602/802 SRAMs utilize a high-performance 2.5VCMOS process, and are packaged in a JEDEC Standard 14mm x20mm 100pin thin plastic quad flatpack (TQFP) as well as a 119 ball gridarray (BGA).

IDT71T75802S100PFI8 Pin Description Summary

Sep.27.21