PC16552DVX/NOPB

PC16552DVX/NOPB Features

Y Dual independent UARTsY Capable of running all existing 16450 and PC16550DsoftwareY After reset� all registers are identical to the 16450 reg-ister setY Read and write cycle times of 84 nsY In the FIFO mode transmitter and receiver are eachbuffered with 16-byte FIFOs to reduce the number ofinterrupts presented to the CPUY Holding and shift registers in the 16450 Mode eliminatethe need for precise synchronization between the CPUand serial dataY Adds or deletes standard asynchronous communicationbits (start� stop� and parity) to or from the serial dataY Independently controlled transmit� receive� line status�and data set interruptsY Programmable baud generators divide any input clockby 1 to (216 b 1) and generate the 16 c clockY MODEM control functions (CTS� RTS� DSR� DTR� RI�and DCD)Y Fully programmable serial-interface characteristics�� 5-� 6-� 7-� or 8-bit characters� Even� odd� or no-parity bit generation and detection� 1-� 1���-� or 2-stop bit generation� Baud generation (DC to 1�5M baud) with 16 c clockY False start bit detectionY Complete status reporting capabilitiesY TRI-STATE� TTL drive for the data and control busesY Line break generation and detectionY Internal diagnostic capabilities�

PC16552DVX/NOPB General Description

The PC16552D is a dual version of the PC16550D UniversalAsynchronous Receiver�Transmitter (UART)� The two serialchannels are completely independent except for a commonCPU interface and crystal input� On power-up both channelsare functionally identical to the 16450�� Each channel canoperate with on-chip transmitter and receiver FIFOs (FIFOmode) to relieve the CPU of excessive software overhead�In FIFO mode each channel is capable of buffering 16 bytes(plus 3 bits of error data per byte in the RCVR FIFO) of datain both the transmitter and receiver� All the FIFO controllogic is on-chip to minimize system overhead and maximizesystem efficiency�Signalling for DMA transfers is done through two pins perchannel (TXRDY and RXRDY)� The RXRDY function is mul-tiplexed on one pin with the OUT 2 and BAUDOUT func-tions� The CPU can select these functions through a newregister (Alternate Function Register)�Each channel performs serial-to-parallel conversion on datacharacters received from a peripheral device or a MODEM�and parallel-to-serial conversion on data characters re-ceived from the CPU� The CPU can read the completestatus of each channel at any time� Status information re-ported includes the type and condition of the transfer opera-tions being performed by the DUART� as well as any errorconditions (parity� overrun� framing� or break interrupt)�The DUART includes one programmable baud rate genera-tor for each channel� Each is capable of dividing the clockinput by divisors of 1 to (216 b 1)� and producing a 16 cclock for driving the internal transmitter logic� Provisions arealso included to use this 16 c clock to drive the receiverlogic� The DUART has complete MODEM-control capability�and a processor-interrupt system� Interrupts can be pro-grammed to the user’s requirements� minimizing the com-puting required to handle the communications link�The DUART is fabricated using National Semiconductor’sadvanced M2CMOSTM�

PC16552DVX/NOPB 6�0 PIN DESCRIPTIONS

PC16552DVX/NOPB Features

Y Dual independent UARTsY Capable of running all existing 16450 and PC16550DsoftwareY After reset� all registers are identical to the 16450 reg-ister setY Read and write cycle times of 84 nsY In the FIFO mode transmitter and receiver are eachbuffered with 16-byte FIFOs to reduce the number ofinterrupts presented to the CPUY Holding and shift registers in the 16450 Mode eliminatethe need for precise synchronization between the CPUand serial dataY Adds or deletes standard asynchronous communicationbits (start� stop� and parity) to or from the serial dataY Independently controlled transmit� receive� line status�and data set interruptsY Programmable baud generators divide any input clockby 1 to (216 b 1) and generate the 16 c clockY MODEM control functions (CTS� RTS� DSR� DTR� RI�and DCD)Y Fully programmable serial-interface characteristics�� 5-� 6-� 7-� or 8-bit characters� Even� odd� or no-parity bit generation and detection� 1-� 1���-� or 2-stop bit generation� Baud generation (DC to 1�5M baud) with 16 c clockY False start bit detectionY Complete status reporting capabilitiesY TRI-STATE� TTL drive for the data and control busesY Line break generation and detectionY Internal diagnostic capabilities�� Loopbackcontrolsforcommunicationslinkfaultisolation� Break� parity� overrun� framing error simulationY Full prioritized interrupt system controls�Can also be reset to 16450 Mode under software control��Note� This part is patented�TRI-STATE� is a registered trademark of National Semiconductor CorporationM2CMOSTM is a trademark of National Semiconductor CorporationC1995 National Semiconductor CorporationRRD-B30M75�Printed in U� S� A�

PC16552DVX/NOPB General Description

The PC16552D is a dual version of the PC16550D UniversalAsynchronous Receiver�Transmitter (UART)� The two serialchannels are completely independent except for a commonCPU interface and crystal input� On power-up both channelsare functionally identical to the 16450�� Each channel canoperate with on-chip transmitter and receiver FIFOs (FIFOmode) to relieve the CPU of excessive software overhead�In FIFO mode each channel is capable of buffering 16 bytes(plus 3 bits of error data per byte in the RCVR FIFO) of datain both the transmitter and receiver� All the FIFO controllogic is on-chip to minimize system overhead and maximizesystem efficiency�Signalling for DMA transfers is done through two pins perchannel (TXRDY and RXRDY)� The RXRDY function is mul-tiplexed on one pin with the OUT 2 and BAUDOUT func-tions� The CPU can select these functions through a newregister (Alternate Function Register)�Each channel performs serial-to-parallel conversion on datacharacters received from a peripheral device or a MODEM�and parallel-to-serial conversion on data characters re-ceived from the CPU� The CPU can read the completestatus of each channel at any time� Status information re-ported includes the type and condition of the transfer opera-tions being performed by the DUART� as well as any errorconditions (parity� overrun� framing� or break interrupt)�The DUART includes one programmable baud rate genera-tor for each channel� Each is capable of dividing the clockinput by divisors of 1 to (216 b 1)� and producing a 16 cclock for driving the internal transmitter logic� Provisions arealso included to use this 16 c clock to drive the receiverlogic� The DUART has complete MODEM-control capability�and a processor-interrupt system� Interrupts can be pro-grammed to the user’s requirements� minimizing the com-puting required to handle the communications link�The DUART is fabricated using National Semiconductor’sadvanced M2CMOSTM�