74ABT162500DLRG4

74ABT162500DLRG4 description

These 18-bit universal bus transceivers combineD-type latches and D-type flip-flops to allow dataflow in transparent, latched, and clocked modes.Data flow in each direction is controlled byoutput-enable (OEAB and OEBA), latch-enable(LEAB and LEBA), and clock (CLKAB andCLKBA) inputs.For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, theA data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in thelatch/flip-flop on the high-to-low transition of CLKAB. Output-enable OEAB is active high. When OEAB is high,the outputs are active. When OEAB is low, the outputs are in the high-impedance state.Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables arecomplementary (OEAB is active high and OEBA is active low).The B-port outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Wto reduce overshoot and undershoot.series resistors

74ABT162500DLRG4 description (continued)

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistorand OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined bythe current-sinking/current-sourcing capability of the driver.The SN54ABT162500 is characterized for operation over the full military temperature range of –55°C to 125°C.The SN74ABT162500 is characterized for operation from –40°C to 85°C.