IDT71V3556S150BG

IDT71V3556S150BG Features

(3.2 ns Clock-to-Data Access)cyclesneed to control OEsignal registers for fully pipelined applicationscompliant)flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitchball grid array (fBGA)

IDT71V3556S150BG Description

The IDT71V3556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMS. They are designed to eliminate dead buscycles when turning the bus around between reads and writes, orwrites and reads. Thus, they have been given the name ZBTTM, orZero Bus Turnaround.Address and control signals are applied to the SRAM during oneclock cycle, and two cycles later the associated data cycle occurs, be itread or write.The IDT71V3556/58 contain data I/O, address and control signalregisters. Output enable is the only asynchronous signal and can be usedto disable the outputs at any given time.A Clock Enable (CEN) pin allows operation of the IDT71V3556/58to be suspended as long as necessary. All synchronous inputs areignored when (CEN) is high and the internal device registers will holdtheir previous values.There are three chip enable pins (CE1, CE2, CE2) that allow the userto deselect the device when desired. If any one of these three are notasserted when ADV/LD is low, no new memory operation can beinitiated. However, any pending data transfers (reads or writes) will becompleted. The data bus will tri-state two cycles after chip is deselectedor a write is initiated.

IDT71V3556S150BG Description continued

The IDT71V3556/58 has an on-chip burst counter. In the burstmode, the IDT71V3556/58 can provide four cycles of data for a singleaddress presented to the SRAM. The order of the burst sequence isdefined by the LBO input pin. The LBO pin selects between linear andinterleaved burst sequence. The ADV/LD signal is used to load a newexternal address (ADV/LD = LOW) or increment the internal burst counter(ADV/LD = HIGH).The IDT71V3556/58 SRAMs utilize IDT's latest high-performanceCMOS process and are packaged in a JEDEC standard 14mm x 20mm100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array(BGA) and a 165 fine pitch ball grid array (fBGA).