IDT71V2559S80PFG8

IDT71V2559S80PFG8 Features

(7.5 ns Clock-to-Data Access)cyclesneed to control OEflatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitchball grid array (fBGA)

IDT71V2559S80PFG8 Description

The IDT71V2557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-bit) synchronous SRAMs organized as 128K x 36 / 256K x 18. They aredesigned to eliminate dead bus cycles when turning the bus aroundbetween reads and writes, or writes and reads. Thus they have beengiven the name ZBTTM, or Zero Bus Turnaround.Address and control signals are applied to the SRAM during one clockcycle, and on the next clock cycle the associated data cycle occurs, beit read or write.