9LP525BG-2LF

9LP525BG-2LF Output Features:

•2 - CPU differential low power push-pull pairs •7- SRC differential low power push-pull pairs •1 - CPU/SRC selectable differential low power push-pull pair •1 - SRC/DOT selectable differential low power push-pull pair •5 - PCI, 33MHz •1 - PCI_F, 33MHz free running •1 - USB, 48MHz •1 - REF, 14.318MHz

9LP525BG-2LF Pin Description

9LP525BG-2LF DESCRIPTION

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9LP525BG-2LF Pin Description

PIN #PIN NAMETYPEDESCRIPTION1PCI0/CR#_AI/O3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pairThe power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 viaSMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus addressspace . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 orpair 0 using the CRA#_EN bit located in byte 5 of SMBUs address space.Byte 5, bit 70 = PCI0 enabled (default)1= CRA# enabled. Byte 5, bit 6 controls whether CRA# controls SRC0 or SRC2 pairByte 5, bit 60 = CRA# controls SRC0 pair (default),1= CRA# controls SRC2 pair2VDDPCIPWRPower supply for PCI clocks, nominal 3.3V3PCI1/CR#_BI/O3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pairThe power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 viaSMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus addressspace . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 orpair 4 using the CRB#_EN bit located in byte 5 of SMBUs address space.Byte 5, bit 50 = PCI1 enabled (default)1= CRB# enabled. Byte 5, bit 6 controls whether CRB# controls SRC1 or SRC4 pairByte 5, bit 40 = CRB# controls SRC1 pair (default)1= CRB# controls SRC4 pair4PCI2/TMEI/O3.3V PCI clock output / Trusted Mode Enable(TME) Latched Input. This pin is sampled on power-up as follows0=Overclocking of CPU and SRC allowed1=Overclocking of CPU and SRC NOT allowedAfter being sampled on power-up, this pin becomes a 3.3V PCI Output5PCI3/CFG0I/O3.3V PCI clock output/Configuration Strap. See PCI3 Configuration Table for more information6PCI4/SRC5_ENI/O3.3V PCI clock output / SRC5 pair or PCI_STOP#/CPU_STOP# enable strap. On powerup, the logic value on this pin determines ifthe SRC5 pair is enabled or if CPU_STOP#/PCI_STOP# is enabled (pins 29 and 30). The latched value controls the pin function onpins 29 and 30 as follows0 = PCI_STOP#/CPU_STOP#1 = SRC5/SRC5#7PCI_F5/ITP_ENI/OFree running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. Onpowerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair.0 =SRC8/SRC8#1 = ITP/ITP#8GNDPCIPWRGround pin for the PCI outputs9VDD48PWRPower pin for the 48MHz output and PLL.3.3V10USB_48MHz/FSLAI/O3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / Fixed48MHz USB clock output. 3.3V.11GND48PWRGround pin for the 48MHz outputs12VDD96_IOPWRPower supply for DOT96 clocks, nominal 0.8V from source/emitter of external pass transistor.13DOTT_96/SRCT0OUTTrue clock of low power differential SRC or DOT96. The power-up default function is SRC0. After powerup, this pin function may bechanged to DOT96 via SMBus Byte 1, bit 7 as follows:0= SRC01=DOT9614DOTC_96/SRCC0OUTComplement clock of low power differential SRC or DOT96. The power-up default function is SRC0#. After powerup, this pinfunction may be changed to DOT96# via SMBus Byte 1, bit 7 as follows0= SRC0#1=DOT96#15GNDPWRGround pin.16VDDPWRPower supply, nominal 3.3V17SRCT1/SE1OUTTrue clock of low power differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -0.5%downspread. The pin function may be changed via SMBus B1b[4:1]18SRCC1/SE2OUTComplement clock of push-pull differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1]19GNDPWRGround pin.20VDDPLL3_IOPWRPower supply for PLL3. 0.8V nominal from source/emitter of external pass transistor21SRCT2/SATATOUTTrue clock of low power differentiall SRC/SATA clock pair.22SRCC2/SATACOUTComplement clock of differential push-pull SRC/SATA clock pair.23GNDSRCPWRGround pin for the SRC outputs

9LP525BG-2LF Pin Description (continued)

PIN #PIN NAMETYPEDESCRIPTION25SRCC3/CR#_DI/OComplementary clock of differential SRC clock pair/ Clock Request control D for either SRC1 or SRC4 pairThe power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4via SMBus. Before configuring this pin as a Clock Request Pin, the SRC output must first be disabled in byte 4, bit 7 of SMBusaddress space . After the SRC output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 1 orpair 4 using the CRD#_EN bit located in byte 5 of SMBUs address space.Byte 5, bit 10 = SRC3 enabled (default)1= CRD# enabled. Byte 5, bit 0 controls whether CRD# controls SRC1 or SRC4 pairByte 5, bit 00 = CRD# controls SRC1 pair (default),1= CRD# controls SRC4 pair26VDDSRC_IOPWRPower supply for SRC clocks. 0.8V nominal from source/emitter of external pass transistor27SRCT4OUTTrue clock of low power differential SRC clock pair.28SRCC4OUTComplement clock of low power differential SRC clock pair.29CPU_STOP#/SRCC5I/ORef, XTAL power supply, nominal 3.3V30PCI_STOP#/SRCT5I/OStops all PCICLKs at logic 0 level, when low. Free running PCICLKs are not effected by this input. / True clock of differential push-pull SRC pair.31VDDSRCPWRSupply for SRC PLL, 3.3V nominal32SRCC6OUTComplement clock of low power differential SRC clock pair.33SRCT6OUTTrue clock of low power differential SRC clock pair.34GNDSRCPWRGround pin for the SRC outputs35SRCC7/CR#_EI/OComplement clock of differential push-pull SRC clock pair. / Clock Request control E for SRC6 pair. The power-up default isSRC7#, but this pin may also be used as a Clock Request control of SRC6 via SMBus. Before configuring this pin as a ClockRequest Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output isdisabled (high-Z), the pin can then be set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configurationspaceByte 6, bit 70 = SRC7# enabled (default)1= CRE# enabled.36SRCT7/CR#_FI/OTrue clock of differential push-pull SRC clock pair/ Clock Request control 8 for SRC8 pairThe power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via SMBus. Before configuringthis pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space After theSRC output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC8 pair using byte 6, bit 6 of SMBusconfiguration space.Byte 6, bit 60 = SRC7# enabled (default)1 = CRF# enabled.37VDDSRC_IOPWRPower supply for SRC clocks. 0.8V nominal from source/emitter of external pass transistor38CPUC2_ITP/SRCC8OUTComplement clock of low power differential CPU2/Complement clock of differential SRC pair. The function of this pin is determinedby the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:Pin 7 latched input Value0 = SRC8#1 = ITP#39CPUT2_ITP/SRCT8OUTTrue clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is determined by the latchedinput value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:Pin 7 latched input Value0 = SRC81 = ITP40VOUTPWROP Amp comparator output. This pin drives the base/gate of the external pass transistor41VDDCPU_IOPWRSupply for CPU clocks. 0.8V nominal from source/emitter of external pass transistor42CPUC1_FOUTComplementary clock of low power differential push-pull CPU output. This CPU clock is free running during iAMT.43CPUT1_FOUTTrue clock of differential push-pull CPU clock pair. This clock is free running during iAMT.44GNDCPUPWRGround pin for the CPU outputs45CPUC0OUTComplement clock of low power differential CPU clock pair.46CPUT0OUTTrue clock of low power differential CPU clock pair.47VDDCPUPWRSupply for CPU PLL, 3.3V nominal48CK_PWRGD/PD#INNotifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode49FSLB/TEST_MODEIN3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values.TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test ClarificationTable.50GNDREFPWRGround pin for the REF outputs.51X2OUTCrystal output, Nominally 14.318MHz52X1INCrystal input, Nominally 14.318MHz.53VDDREFPWRRef, XTAL power supply, nominal 3.3V54REF0/FSLC/TEST_SELI/O14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FSand Vih_FS values. /TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table55SDATAI/OData pin for SMBus circuitry, 5V tolerant.56SCLKINClock pin of SMBus circuitry, 5V tolerant.