9EX21801AKILFT

9EX21801AKILFT Features/Benefits

•Supports output clock frequencies up to 400 MHz •4 Selectable SMBus addresses •SMBus address is independent of PLL operating mode •Dedicated CKPWRGD/PD# and VDDA pins ease boarddesign •Available in industrial temperature range (-40°C to +85°C)

9EX21801AKILFT Description

The 9EX21801 provides 18 output clocks for PCIe Gen2(100MHz) or QPI (133MHz) applications. The 9EX21801 has 4selectable SMBus addresses, and dedicated CKPWRGD/PD#and VDDA pins for easy board design. A differential CPU clockfrom a CK410B+ main clock generator, such as the 932S421,drives the 9EX21801. In fanout mode, the 9EX21801 providesoutputs up to 400MHz.

9EX21801AKILFT Pin Description

PIN #PIN NAMEPIN TYPEDESCRIPTION1VDDPWRPower supply, nominal 3.3V2OE10#INActive low input for enabling DIF pair 10.1 = tri-state outputs, 0 = enable outputs3DIF_10OUT0.7V differential true clock output4DIF_10#OUT0.7V differential complement clock output5OE11#INActive low input for enabling DIF pair 11.1 = tri-state outputs, 0 = enable outputs6DIF_11OUT0.7V differential true clock output7DIF_11#OUT0.7V differential complement clock output8OE12#INActive low input for enabling DIF pair 12.1 = tri-state outputs, 0 = enable outputs9DIF_12OUT0.7V differential true clock output10DIF_12#OUT0.7V differential complement clock output11GNDPWRGround pin.12VDDPWRPower supply, nominal 3.3V13DIF_13OUT0.7V differential true clock output14DIF_13#OUT0.7V differential complement clock output15OE13#INActive low input for enabling DIF pair 13.1 = tri-state outputs, 0 = enable outputs16DIF_14OUT0.7V differential true clock output17DIF_14#OUT0.7V differential complement clock output18OE14#INActive low input for enabling DIF pair 14.1 = tri-state outputs, 0 = enable outputs19DIF_15OUT0.7V differential true clock output20DIF_15#OUT0.7V differential complement clock output21VDDPWRPower supply, nominal 3.3V22OE15_17#INActive low input for enabling DIF pairs 15, 16 and 171 = tri-state outputs, 0 = enable outputs23DIF_16OUT0.7V differential true clock output24DIF_16#OUT0.7V differential complement clock output25DIF_17OUT0.7V differential true clock output26DIF_17#OUT0.7V differential complement clock output27IREFOUTThis pin establishes the reference current for the differential current-mode output pairs. This pinrequires a fixed precision resistor tied to ground in order to establish the appropriate current. 475ohms is the standard value.28GNDAPWRGround pin for the PLL core.29VDDAPWR3.3V power for the PLL core.30CLKA_ININTrue Input for differential reference clock.31CLKA_IN#INComplement Input for differential reference clock.32GNDPWRGround pin.33CLKB_ININTrue Input for differential reference clock.34CLKB_IN#INComplement Input for differential reference clock.35VDDPWRPower supply, nominal 3.3V36OE_01234#INActive low input for enabling DIF pairs 0, 1, 2, 3 and 4.1 = tri-state outputs, 0 = enable outputs