9DB823BFLFT

9DB823BFLFT Features/Benefits

• Spread spectrum modulation tolerant, 0 to -0.5% downspread and +/- 0.25% center spread • Supports undriven differential outputs in Power Downand DIF_STOP# modes for power management.

9DB823BFLFT General Description

The ICS9DB823B is compatible with the Intel DB800QDifferential Buffer Specification. This buffer provides 8PCI-Express SRC or 8 QPI clocks. The ICS9DB823B isdriven by a differential output pair from a CK410B+ orCK509B main clock generator.

9DB823BFLFT Pin Descriptions for OE_INV=0

PIN #PIN NAMEPIN TYPEDESCRIPTION12SRC_DIV#VDDR3 GND45SRC_INSRC_IN#6 OE_07 OE_38 DIF_09 DIF_0#10 GND11 VDD12 DIF_113 DIF_1#14 OE_115 OE_216 DIF_217 DIF_2#18 GND19 VDD20 DIF_321 DIF_3#INPWRPWRININININOUTOUTPWRPWROUTOUTININOUTOUTPWRPWROUTOUTActive low Input for determining SRC output frequency SRC or SRC/2.0 = SRC/2, 1= SRC3.3V power for differential input clock (receiver). This VDD should be treated asan analog power rail and filtered appropriately.Ground pin.0.7 V Differential SRC TRUE input0.7 V Differential SRC COMPLEMENTARY inputActive high input for enabling output 0.0 =disable outputs, 1= enable outputsActive high input for enabling output 3.0 =disable outputs, 1= enable outputs0.7V differential true clock output0.7V differential Complementary clock outputGround pin.Power supply, nominal 3.3V0.7V differential true clock output0.7V differential Complementary clock outputActive high input for enabling output 1.0 =disable outputs, 1= enable outputsActive high input for enabling output 2.0 =disable outputs, 1= enable outputs0.7V differential true clock output0.7V differential Complementary clock outputGround pin.Power supply, nominal 3.3V0.7V differential true clock output0.7V differential Complementary clock output22 BYPASS#_133_100INInput to select Bypass(fan-out), QPI PLL (133MHz) or PCIe PLL (100MHz) mode0 = Bypass mode, M= QPI, 1= PCIe PLL mode23 SCLK24 SDATAINI/OClock pin of SMBus circuitry, 5V tolerant.Data pin for SMBus circuitry, 5V tolerant.