9DB233AGF

9DB233AGF Output Features

• 2 - 0.7V current mode differential HCSL output pairs

9DB233AGF Description

The 9DB233 zero-delay buffer supports PCIe Gen3requirements, while being backwards compatible to PCIeGen2 and Gen1. The 9DB233 is driven by a differentialSRC output pair from an IDT 932S421 or 932SQ420 orequivalent main clock generator. It attenuates jitter on theinput clock and has a selectable PLL bandwidth tomaximize performance in systems with or withoutSpread-Spectrum clocking. An SMBus interface allowscontrol of the PLL bandwidth and bypass options, while 2clock request (OE#) pins make the 9DB233 suitable forExpress Card applications.

• OE# pins; suitable for Express Card applications

9DB233AGF Pin Descriptions

Note:Pins preceeded by ' v ' have internal 120K ohm pull down resistors