97U870AKLFT

97U870AKLFT Pin Descriptions

AGNDGNDNBThe PLL clock buffer, ICS97U870,levels.Package optionsincludea plastic52-ballVFBGA and a 40-pin MLF.is designedfor a Vooa of 1.8V, a AVoo of 1.8V and differentialdata input and output(CLKT[0:9],are controlledpins (OE, OS) and the Analog Power input (AVDD). When OE is low, theCLKC[0:91)by the inputclocks(CLK_INT,(FB_ OUTT, FBOUTC).(FB_INT,the feedback clockspair feedbackclock outputsCLK_INC),FB_INC), thea differentialand one differentialis a zero delay buffer that distributesICS97U870pair of clock outputsThe clock outputsLVCMOS programwhile the internalFB_OUTC) are disabledpin that must be tied to GND orVooa.programOE has no effect on CLKT7 /CLKC7 (they are free runningthe PLL is turned off and bypassedfor test purposes.PLL continuesto maintainWhen OS is high, OE will functionits locked-inoutputsfrequency.FB_ OUTT/(exceptOS (OutputSelect)above. When OS is low,When AVoo is grounded,as describedis aclock input pair (CLK_INT,CLK_INC)to ten differentialin additionto FB _ OUTT /FB _ OUTC).CLK_INC)(CLK_INT,on the differentialWhen both clock signalsdetectioncircuita low power state where all outputs,low to being differential signals,will obtainwithinthe feedbacktime tsrAB,stabilizationphase lock betweenthe specifiedthe feedbackinputs,independentare logic low, the device will enter a low power mode. An input logicwill detectand the PLL are OFF. When the inputsthe logic low level and performtransitionfrom the input buffers,from both being logicthe PLL will be turned back on, the inputsand outputswill be enabledand the PLLclock pair (FB_INT, FB_INC)and the input clock pair (CLK_INT,CLK_INC)The PLL in ICS97U870FB _INC) to provideis also able to track Spread Spectrumuses the input clockslow-skew,Clocking(FB_INT,low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]).ICS97U870(SSC) for reducedhigh-performance,and the feedback(CLK_INT,clock driverCLK_INC)clocksEMI.ICS97U870is characterizedfor operationfrom 0°C to 70°C.2