95V850AGLFT

95V850AGLFT Product Description/Features:

•Low skew, low jitter PLL clock driver •Feedback pins for input to output synchronization •Spread Spectrum tolerant inputs •With bypass mode mux •Operating frequency 60 to 210 MHz •AC Coupled (Universal) CLK inputs:- 400 mV switching amplitude- (LVTTL, LVPELL, LVDS, LVCMOS) standardstranslation to SSTL2

95V850AGLFT Product Description/Features:

•Low skew, low jitter PLL clock driver •Feedback pins for input to output synchronization •Spread Spectrum tolerant inputs •With bypass mode mux •Operating frequency 60 to 210 MHz •AC Coupled (Universal) CLK inputs:- 400 mV switching amplitude- (LVTTL, LVPELL, LVDS, LVCMOS) standardstranslation to SSTL2

95V850AGLFT Pin Descriptions

95V850AGLFT Pin Descriptions

PIN NUMBERPIN NAMETYPEESCRIPTIOND1, 7, 8, 18, 24, 25,31, 41, 42, 48GNDPWRroundG26, 30, 40, 43, 47,23, 19, 9, 6, 2CLK[9:0]OUToutpu stp rialaitffid erenolc cks ofCom elp mentary""27, 29, 39, 44, 46,22, 20, 10, 5, 3CLK[9:0]OUToutpu striaplaiterenffidTrue" C ol ck of"4, 11, 21, 28,34, 38, 45,VDDPWR2.5V,ylpower supP13CLK_INTINolc ck ni putTrue" reference"14CLK_INCINolc ck ni putCom elp mentary" reference"16AVDDPWR2.5V,ylpg power supolanA17AGNDPWRg groundolanA32FB_OUTCOUTtI.kfla eedbac"Com elp mentary" Feedback outpu ,t de cid ated for e tx ernoutput mu ts be w ri edsw cti hes at the same rf equency as the CLK. T siho FB_INCt33FB_OUTTOUTsw cti hestI.kfla eedbac"True" " Feedback outpu ,t de cid ated for e tx ernoutput mu ts be w ri ed toat the same rf equency as the CLK. T sihB_INTF35FB_INTINtla o the ni tern la PLL forgis n"True" Feedback ni pu ,t pro div es feedbackile m ni ate phase e rr orynchro zin a oit n w ti h CLK_INT tos36FB_INCINtla o the ni tern la PLLgis n"Com elp mentary" Feedback ni pu ,t pro div esile m ni ate phase e rr oror synchro zin a oit n w ti h CLK_INC tof12, 15, 37NCo Conne stcN