951462AGLF

951462AGLF Output Features:

•2 - pairs of CPU pairs •8 - pairs of SRC pairs •4 - pairs of ATIG pairs •1 - HyperTransport 66MHz clock seed •2 - 48MHz USB clock •3 - 14.318MHz Reference clock

951462AGLF Description

951462AGLF Pin Description

951462AGLF Pin Description (Continued)

951462AGLF Pin Description

PIN #PIN NAMETYPEDESCRIPTION1GNDREFPWRGround pin for the REF outputs.2VDDREFPWRRef, XTAL power supply, nominal 3.3V3X1INCrystal input, Nominally 14.318MHz.4X2OUTCrystal output, Nominally 14.318MHz5VDD48PWRPower pin for the 48MHz output.3.3V648MHz_0OUT48MHz clock output.748MHz_1OUT48MHz clock output.8GND48PWRGround pin for the 48MHz outputs9SMBCLKINClock pin of SMBUS circuitry, 5V tolerant10SMBDATI/OData pin of SMBUS circuitry, 5V tolerant11RESET_IN#INReal time active low input. When active, SMBus is reset to power updefault.12SRCCLKT7OUTTrue clock of differential SRC clock pair.13SRCCLKC7OUTComplement clock of differential SRC clock pair.14VDDSRCPWRSupply for SRC clocks, 3.3V nominal15GNDSRCPWRGround pin for the SRC outputs16SRCCLKT6OUTTrue clock of differential SRC clock pair.17SRCCLKC6OUTComplement clock of differential SRC clock pair.18SRCCLKT5OUTTrue clock of differential SRC clock pair.19SRCCLKC5OUTComplement clock of differential SRC clock pair.20SRCCLKT4OUTTrue clock of differential SRC clock pair.21SRCCLKC4OUTComplement clock of differential SRC clock pair.22GNDSRCPWRGround pin for the SRC outputs23VDDSRCPWRSupply for SRC clocks, 3.3V nominal24SRCCLKT3OUTTrue clock of differential SRC clock pair.25SRCCLKC3OUTComplement clock of differential SRC clock pair.26SRCCLKT2OUTTrue clock of differential SRC clock pair.27SRCCLKC2OUTComplement clock of differential SRC clock pair.28VDDSRCPWRSupply for SRC clocks, 3.3V nominal29GNDSRCPWRGround pin for the SRC outputs30ATIGCLKT3OUTTrue clock of differential ATIGCLK clock pair.31ATIGCLKC3OUTComplementary clock of differential ATIGCLK clock pair.32*CLKREQB#INOutput enable for PCI Express (SRC) outputs. SMBus selects whichoutputs are controlled.0 = enabled, 1 = tri-stated

951462AGLF Pin Description (Continued)

PIN #PIN NAMETYPEDESCRIPTION33*CLKREQC#INOutput enable for PCI Express (SRC) outputs. SMBus selects whichoutputs are controlled.0 = enabled, 1 = tri-stated34ATIGCLKC2OUTComplementary clock of differential ATIGCLK clock pair.35ATIGCLKT2OUTTrue clock of differential ATIGCLK clock pair.36ATIGCLKC1OUTComplementary clock of differential ATIGCLK clock pair.37ATIGCLKT1OUTTrue clock of differential ATIGCLK clock pair.38GNDATIGPWRGround for ATIG clocks39VDDATIGPWRPower supply ATIG clocks, nominal 3.3V40ATIGCLKC0OUTComplementary clock of differential ATIGCLK clock pair.41ATIGCLKT0OUTTrue clock of differential ATIGCLK clock pair.42SRCCLKC1OUTComplement clock of differential push-pull SRC clock pair.43SRCCLKT1OUTTrue clock of differential SRC clock pair.44VDDSRCPWRSupply for SRC clocks, 3.3V nominal45GNDSRCPWRGround pin for the SRC outputs46SRCCLKC0OUTComplement clock of differential SRC clock pair.47SRCCLKT0OUTTrue clock of differential SRC clock pair.48IREFOUTThis pin establishes the reference current for the differential current-modeoutput pairs. This pin requires a fixed precision resistor tied to ground inorder to establish the appropriate current. 475 ohms is the standard value.49GNDAPWRGround pin for the PLL core.50VDDAPWR3.3V power for the PLL core.51CPUCLK8C1OUTComplementary clock of differential 3.3V push-pull K8 pair.52CPUCLK8T1OUTTrue clock of differential 3.3V push-pull K8 pair.53GNDCPUPWRGround pin for the CPU outputs54VDDCPUPWRSupply for CPU clocks, 3.3V nominal55CPUCLK8C0OUTComplementary clock of differential 3.3V push-pull K8 pair.56CPUCLK8T0OUTTrue clock of differential 3.3V push-pull K8 pair.57*CLKREQA#INOutput enable for PCI Express (SRC) outputs. SMBus selects whichoutputs are controlled.0 = enabled, 1 = tri-stated58GNDHTTPWRGround pin for the HTT outputs59HTTCLK0OUT3.3V Hyper Transport output60VDDHTTPWRSupply for HTT clocks, nominal 3.3V.61PD**INAsynchronous active high input pin used to power down the device. Theinternal clocks are disabled and the VCO is stopped.62FS2/REF2I/OFrequency select latch input pin / 14.318 MHz reference clock.63FS1/REF1I/OFrequency select latch input pin / 14.318 MHz reference clock.64FS0/REF0I/OFrequency select latch input pin / 14.318 MHz reference clock.