82V3910AUG8

82V3910AUG8 FEATURES

HIGHLIGHTS • • • • • • • • • • • • •MAIN FEATURES •Jitter generation <0.3 ps RMS (10 kHz to 20 MHz), meets jitter gen-eration requirements of leading PHYs supporting 10GBASE-R,10GBASE-W, 40GBASE-R, OC-192 and STM-64Features 0.5 mHz to 35 Hz bandwidthProvides node clock for ITU-T G.8261/G.8262 Synchronous Ether-net (SyncE)Provides node clocks for Cellular and WLL base-station (GSM and3G networks)Provides clocks for DSL access concentrators (DSLAM), especiallyfor Japan TCM-ISDN network timing based ADSL equipmentsProvides clocks for 1 Gigabit, 10 Gigabit, and 40 Gigabit EthernetSupports clock generation for IEEE-1588 applicationsProvides an integrated solution for Synchronous Equipment TimingSource, including Stratum 3, SMC, EEC-Option 1 and EEC-Option 2 ClocksIntegrates T4 DPLL and T0 DPLL; T4 DPLL locks independently orlocks to T0 DPLLSupports programmable DPLL bandwidth (0.5 mHz to 35 Hz) anddamping factor (1.2 to 20 in 5 steps)Supports 1.1X10-5 ppm absolute holdover accuracy and4.4X10-8 ppm instantaneous holdover accuracySupports hitless reference switching to minimize phase transientson T0 DPLL output to be no more than 0.61 nsIntegrates 2 jitter attenuating APLLs to generate ultra-low jitterclocks • Supports 3 clock modes: SONET, Ethernet, and Ethernet LAN-PHY • Supports up to two crystal connections, allowing each APLL tosupport up to two modes of operationSupports input and output clocks whose frequencies range from1PPS to 644.53125 MHz • • ProvidesIncludes 1PPS clock input and output64 kHz + 8 kHzand64 kHz + 8 kHz + 0.4 kHz composite clocksIN1IN2foror • Provides IN3, IN4, IN7~IN14 input CMOS clocks whose frequen-cies range from 1PPS to 156.25 MHz • Provides IN5 and IN6 input differential clocks whose frequenciesrange from 1PPS to 625 MHz • Provides OUT1 to OUT5 output CMOS clocks whose frequencycover from 1PPS to 125 MHz • Provides OUT6,OUT7,OUT10 and OUT11 output differentialclocks whose frequency cover from 25 MHz to 644.53125 MHz • Provides OUT8 for composite clocks and OUT9 for 1.544 MHz/2.048 MHz (BITS/SSU)Provides output clocks for BITS, GPS, 3G, GSM, etc.Provides a 1PPS, 2 kHz, 4 kHz, or 8 kHz frame sync input signal,and a 1PPS, 2 kHz or 8 kHz frame sync output signalInternal DCO can be controlled by an external processor to be usedfor IEEE-1588 clock generationSupports programmable input-to-output phase offset adjustmentLimits the phase and frequency offset of the outputsSupports Forced or Automatic operating mode switch controlled byan internal state machine. Automatic mode switch supports Free-Run, Locked and Holdover modesSupports manual and automatic selected input clock switchSupports automatic hitless selected input clock switch on clock fail-ureSupports three types of input clock sources: recovered clock fromSTM-N or OC-n, PDH network synchronization timing and externalsynchronization reference timingSupports AMI, LVPECL/LVDS and CMOS input/output technologiesSupports Master/Slave application (two chips used together) toenable system protection against single chip failureSupports Telcordia GR-1244-CORE, Telcordia GR-253-CORE,ITU-T G.812, ITU-T G.8262, ITU-T G.813 and ITU-T G.783 Recom-mendations • • • • • • • • • • • •OTHER FEATURES • • • •I2C Microprocessor interfaceIEEE 1149.1 JTAG Boundary ScanSingle 3.3 V operation with 5 V tolerant CMOS I/Os1mm ball pitch CABGA green package

82V3910AUG8 APPLICATIONS

• • • • • •SMC / SEC (SONET / SDH equipment)EEC (Synchronous Ethernet equipment)Core and access IP switches / routersGigabit and Terabit IP switches / routersCellular and WLL base-station node clocksBroadband and multi-service access equipment

82V3910AUG8 DESCRIPTION

The 82V3910 Synchronous Ethernet (SyncE) SETS meets therequirements of ITU-T G.8262/G.813 for EEC/SEC options 1 and 2; andit meets the requirements of Telcordia GR-253-CORE Stratum 3 (S3)and SONET Minimum Clock (SMC). The 82V3910 ultra-low jitter outputclocks can be used to directly synchronize 10GBASE-R/10GBASE-Wand OC-192/STM-64 PHYs and 40GBASE-R PHYs in SynchronousEthernet and SONET/SDH equipment.The Synchronous Equipment Timing Source (SETS) functions areprovided by two independent digital PLLs (DPLLs), T0 and T4, each withembedded clock synthesizers. The T0 DPLL meets the network syn-chronization requirements for frequency accuracy, pull-in, hold-in, pull-out, noise generation, noise tolerance, transient response and holdoverperformance. The T4 DPLL provides rate conversion functions that canbe used, for example, to convert a recovered line clock to a 1.544 MHz,2.048MHz or 64 kHz synchronization reference for external equipment.The 82V3910 provides ten single ended reference inputs and two dif-ferential reference inputs that can operate at common Ethernet, SONET/SDH and PDH frequencies and other frequencies. The device also pro-vides two Alternate Mark Inversion (AMI) inputs for Composite Clock(CC) signals bearing 64 kHz, 8 kHz and 0.4 kHz synchronization infor-mation. The references are continually monitored for loss of signal andfor frequency offset per user programmed thresholds. All of the refer-ences are available to both digital PLLs (DPLLs). The active referencefor each DPLL is determined by forced selection or by automatic selec-tion based on user programmed priorities and locking allowances andbased on the reference monitors.The 82V3910 can accept a clock reference and a phase lockedexternal sync signal as a pair. The T0 DPLL can lock to the referenceclock input and align its frame sync and multi-frame sync outputs withthe paired external sync input. The device provides to two external syncinputs that can be associated with any of the twelve reference inputs tocreate up to two pairs. The external sync signals can have a frequencyof 1 Hz, 2 kHz or 8 kHz. This feature enables the T0 DPLL to phasealign its frame sync and multi-frame sync outputs with an external syncinput without the need use a low bandwidth setting to lock directly to anexternal sync input.Both DPLLs support four primary operating modes: Free-Run,Locked, Holdover and Digitally Controlled Oscillator (DCO) Control. InFree-Run mode the DPLLs generate clocks based on the master clockalone. In Locked mode the DPLLs filter reference clock jitter with theselected bandwidth. In Locked mode the long-term DPLL frequencyaccuracy is the same as the long term frequency accuracy of theselected input reference. In Holdover mode the DPLL uses frequencydata acquired while in Locked mode to generate accurate frequencieswhen input references are not available. In DCO Control Mode the DPLLcontrol loop is opened and the DCO can be used by an algorithm (e.g.IEEE 1588 clock servo) running on an external processor to synthesizeclock signals.The 82V3910 requires a 12.8 MHz master clock for its referencemonitors and other digital circuitry. The frequency accuracy of the mas-ter clock determines the frequency accuracy of the DPLLs in Free-Runmode. The frequency stability of the master clock determines the fre-quency stability of the DPLLs in Free-Run mode and in Holdover mode.The T0 DPLL can be configured with a range of selectable filteringbandwidths from 0.5 mHz to 35 Hz. The 15 mHz and lower bandwidthscan be used to lock the T0 DPLL directly to a 1 pulse per second (PPS)reference. The 0.1 Hz bandwidth can be used for G.8262/G.813 Option2 or Telcordia GR-253-CORE S3 or SMC applications. The bandwidthsin the range 1.2 Hz to 8 Hz can be used for G.8262/G.813 Option 1applications. The bandwidths 18 Hz and 35 Hz can be used in jitterattenuation and rate conversion applications.The T4 DPLL can be configured with filtering bandwidths of 18Hz or35 Hz.The clocks synthesized by the 82V3910 DPLLs can be passedthrough either of the two independent voltage controlled crystal oscillator(VCXO) based jitter attenuating analog PLLs (APLLs). Both APLLs drivetwo independent dividers that have differential outputs. The APLLs useexternal crystal resonators with resonant frequencies equal to the APLLbase frequency divided by 25. Both APLLs can be provisioned with oneor two selectable crystal resonators to support up to two base frequen-cies per APLL. The output clocks generated by the APLLs exhibit jitterbelow 0.30ps RMS over the integration range 10 kHz to 20 MHz for mostoutput frequencies.Any of the 82V3910 DPLL clocks can be routed through a mux to anyof five single ended outputs via independent output dividers. The outputof the T0 DPLL can be routed through the two auto-dividers to the singleended frame sync output that operates at 8 kHz or 1 PPS,