650R-07LF

650R-07LF Features

DATASHEET

650R-07LF Description

650R-07LF Pin Descriptions

PinNamePin TypeDescription1234567891011121314151617181920ACS0Tri-level Input A clock select 0. Selects outputs on CLKA1 and CLKA2. See table below.X2X1/ICLKVDDACS1GNDCLKC1CLKC2CLKB2CLKB1CCSDCXOXICrystal connection. Connect to a crystal or leave unconnected for clock input.Crystal connection. Connect to fundamental crystal or clock input.PowerConnect to 3.3 V or 5 V. Must be same value as other VDD.InputA clock select 1. Selects outputs on CLKA1 and CLKA2. Internal pull-upresistor. See table below.PowerConnect to ground.OutputOutputOutputOutputClock C output 1. Depends on setting of CCS per table below.Clock C output 2. Depends on setting of CCS per table below. Same as CLKC1.Clock B output 2. Depends on setting of BCS1, 0 per table below.Clock B output 1. Depends on setting of BCS1, 0 per table below.Tri-level Input Clock C Select pin. Selects outputs on CLKC1 and CLKC2 per table below.—Don’t Connect. Do not connect anything to this pin.CLKA2OutputClock A output 2. Depends on setting of ACS1, 0 per table below.GNDOEVDDCLKA1REFOUTBCS0BCS1PowerConnect to ground.InputOutput enable. Tri-states all outputs when low. Internal pull-up resistor.PowerOutputOutputConnect to VDD. Must be same value as other VDD.Clock A output 1. Depends on setting of ACS1, 0 per table below.Buffered reference clock output. Same frequency as crystal or clock input.Tri-level Input B clock select 0. Selects outputs on CLKB1 and CLKB2. See table below.InputB clock select 1. Selects outputs on CLKB1 and CLKB2. See table below.