GTLP6C816MTC

GTLP6C816MTC Features

I Interface between LVTTL and GTLP logic levelsI Designed with edge rate control circuitry to reduce out-put noise on the GTLP portI VREF pin provides external supply reference voltage forreceiver threshold adjustibilityI Special PVT compensation circuitry to provide consis-tent performance over variations of precess, supply volt-age and temperatureI TTL compatible driver and control inputsI Designed using Fairchild advanced CMOS technologyI Bushold data inputs on A port to eliminate the need forexternal pull-up resistors for unused inputsI Power up/down and power off high impedance for liveinsertionI 5V over voltage tolerance on LVTTL portsI Open drain on GTLP to support wired-or connectionI A Port source/sink −24mA/+24mAI B Port sink +50mAI 1:6 fanout clock driver for TTL portI 1:2 fanout clock driver for GTLP port

GTLP6C816MTC General Description

The GTLP6C816 is a clock driver that provides TTL toGTLP signal level translation (and vice versa). The deviceprovides a high speed interface between cards operating atTTL logic levels and a backplane operating at GTLP logiclevels. High speed backplane operation is a direct result ofGTLP’s reduced output swing (<1V), reduced input thresh-old levels and output edge rate control. The edge rate con-trol minimizes bus settling time. GTLP is a FairchildSemiconductor derivative of the Gunning Transceiver logic(GTL) JEDEC standard JESD8-3.Fairchild’s GTLP has internal edge-rate control and is pro-cess, voltage, and temperature (PVT) compensated. Itsfunction is similar to BTL and GTL but with different outputlevels and receiver threshold. GTLP output LOW level istypically less than 0.5V, the output level HIGH is 1.5V andthe receiver threshold is 1.0V.

GTLP6C816MTC Functional Description

The GTLP6C816 is a clock driver providing TTL-to-GTLP clock translation, and GTLP-to-TTL clock translation in the samepackage. The TTL-to-GTLP direction is a 1:2 clock driver path with a single Enable pin (OEB). For the GTLP-to-TTL direc-tion the clock receiver path is a 1:6 buffer with a single Enable control (OEA). Data polarity is inverting for both directions.