DM74S280N

DM74S280N Features

I Generates either odd or even parity for nine data linesI Cascadable for N-bitsI Can be used to upgrade existing systems using MSI par-ity circuitsI Typical data-to-output delay—14 ns

DM74S280N General Description

These universal, nine-bit parity generators/checkers utilizeSchottky-clamped TTL high-performance circuitry, and fea-ture odd/even outputs to facilitate operation of either odd oreven parity applications. The word-length capability is eas-ily expanded by cascading.The DM74S280 can be used to upgrade the performanceof most systems utilizing the DM74180 parity generator/checker. Although the DM74S280 is implemented withoutexpander inputs, the corresponding function is provided bythe availability of all input at pin 4, and no internal connec-tion at pin 3. This permits the DM74S280 to be substitutedfor the 180 in existing designs to produce an identical func-tion, even if DM74S280’s are mixed with existing 180’s.Input buffers are provided so that each input representsonly one normal 74S load, and full fan-out to 10 normalSeries 74S loads is available from each of the outputs atlow logic levels. A fan-out to 20 normal Series 74S loads isprovided at high logic levels, to facilitate connection ofunused inputs to used inputs.

DM74S280N Typical Applications

Three DM74S280’s can be used to implement a 25-lineparity generator/checker. This arrangement will provideparity in typically 25 ns. (See Figure 1.)Longer word lengths can be implemented by cascadingDM74S280’s. As shown in Figure 2, parity can be gener-ated for word lengths up to 81 bits in typically 25 ns.FIGURE 1. 25-Line Parity/Generator CheckerFIGURE 2. 81-Line Parity/Generator Checker