0W344-004-XTP

0W344-004-XTP 1.0 General Description

BelaSigna 200 is a high-performance, programmable, mixed-signal digital signal processor (DSP) that is based onON Semiconductor’s patented second-generation SignaKlara™ technology.This single-chip solution is ideally suited for embedded applications where audio performance, low power consumption andminiaturization are critical. BelaSigna 200 targets a wide variety of digital speech- and audio-centric applications, including:�Communication headsets�Smart phones�Personal digital assistants (PDAs)�Hands-free car kits�Bluetooth™ wireless technology systemsBelaSigna 200 provides numerous analog and digital interfaces including parallel, serial, synchronous, and asynchronous interfaces tofacilitate the connection with transducers from various applications.BelaSigna 200 contains two primary processing blocks, which all work together to provide a complete audio processing chain. Theanalog section includes two 16-bit A/D converters and two 16-bit D/A converters. Two on-chip direct digital output stages allowBelaSigna 200 to drive various output transducers directly, eliminating the need for external power amplifiers.BelaSigna 200 features internal clock generation and power regulation for excellent noise and power performance. Two DSPsubsystems operate concurrently: the RCore, which is a fully programmable DSP core, and the weighted overlap-add (WOLA)filterbank coprocessor, which is a dedicated, configurable processor that executes time-frequency domain transforms and other vector-based computations. In addition to these processors, there are several other peripherals, which optimize the architecture to audioprocessing, such as the onput/output processor (IOP) – an audio-targeted direct memory access (DMA) processor, which runs in thebackground and manages the data flow between the converters and the two processors. The BelaSigna 200 functional block diagram isshown in Figure 1.Figure 1: BelaSigna 200 Functional Block Diagram

0W344-004-XTP 2.0 Key Features

2.1 System • 16-bit programmable fixed-point DSP core • Configurable WOLA filterbank coprocessor optimized for filterbank calculations • 12-Kword program memory (PRAM) • Two 4-Kword data memories (XRAM and YRAM) • Two 384-word dual-port FIFO memories • Two 128-word dual-port 18-bit memories dedicated to WOLA output results • 576-word memory dedicated to WOLA gain values, WOLA windows and other configuration data • Internal oscillator • Operating voltage of 1.8V nominal • Ultra-low power: less than 1mW @ 1.28MHz system clock frequency, 1.8V nominal operating voltage, both processors running • Available in a QFN package; other packages available upon request2.2 RCore DSP • Dual-Harvard architecture, 16-bit programmable fixed-point DSP with three execution units • Single-cycle multiply-accumulate (MAC) with 40-bit accumulator • Highly parallel instruction set with powerful addressing modes • Flexible address generation (including modulo addressing) for accessing program memory and data memories, plus control andconfiguration registers • Separate system and user stacks with dedicated stack pointers • Fast normalization and de-normalization operations optimized for signal level calculation and block-floating point calculations • Supports time-domain pre- and post-processing of input data stream and frequency-domain processing of WOLA output • Master processor for entire system2.3 WOLA Filterbank Coprocessor • Mono and stereo time-frequency transforms providing real or complex data results • Standard library of overlap-add (OLA) and WOLA filterbank configurationsoConfigurable number of frequency bandsoConfigurable number of frequency bandsoConfigurable oversampling and decimation factorsoConfigurable windows • Low group delay (< 4ms for 16 bands possible) • Fast real and complex gain application for magnitude and phase processing • Block floating-point calculations (4-bit exponent, 18-bit mantissa) to achieve high fidelity • Maximum digital gain of 90dB possible • High-fidelity time-frequency domain processing • Low-overhead interaction with the RCore through shared memories, control registers and interrupts2.4 Input Output Processor (IOP) • Block-based DMA for all audio data provides automatic management of input and output FIFOs that reduces processor overhead • Mono (one in, one out), simple stereo (two in, one out), full stereo (two in, two out) and digital mixed (two in, one out) operatingmodes • Interacts with the RCore through interrupts and shared memories • Normal and smart FIFO audio data accessing schemes availableRev. 16 | Page 2 of 43 | www.onsemi.com