N74F273AD,623

N74F273AD,623 Product specification

N74F273AD,623 FEATURES

• High impedance inputs for reduced loading(20µA in Low and High states) • Ideal buffer for MOS microprocessor or memory • Eight edge–triggered D–type flip–flops • Buffered common clock • Buffered asynchronous Master Reset • See 74F377A for clock enable version • See 74F373 for transparent latch version • See 74F374 for 3–State version

N74F273AD,623 DESCRIPTION

The 74F273 has eight edge–triggered D–type flip–flops withindividual D inputs and Q outputs. The common buffered Clock (CP)and Master Reset (MR) inputs load and reset (clear) all flip–flopssimultaneously.The register is fully edge–triggered. The state of each D input, onesetup time before the Low–to–High clock transition, is transferred tothe corresponding flip–flop’s Q output.All outputs will be forced Low independently of Clock or Data inputsby a Low voltage level on the MR input. The device is useful forapplications where the true output only is required and the CP andMR are common to all elements.