N74F109D,602

N74F109D,602 DESCRIPTION

The 74F109 is a dual positive edge-triggered JK-type flip-flopfeaturing individual J, K, clock, set, and reset inputs; also true andcomplementary outputs. Set (SD) and reset (RD) are asynchronousactive low inputs and operate independently of the clock (CP) input.The J and K are edge-triggered inputs which control the statechanges of the flip-flops as described in the function table. Clocktriggering occurs at a voltage level and is not directly related to thetransition time of the positive-going pulse. The J and K inputs mustbe stable just one setup time prior to the low-to-high transition of theclock for predictable operation. The JK design allows operation as aD flip-flop by tying J and K inputs together. Although the clock inputis level sensitive, the positive transition of the clock pulse betweenthe 0.8V and 2.0V levels should be equal to or less than the clock tooutput delay time for reliable operation.

N74F109D,602 Product specification