74HC40103D,652

74HC40103D,652 2. Features and benefits

 Cascadable Synchronous or asynchronous preset Low-power dissipation Complies with JEDEC standard no. 7A CMOS input levels ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +80 C and from 40 C to +125 C

74HC40103D,652 1. General description

The 74HC40103 is an 8-bit synchronous down counter. It has control inputs for enablingor disabling the clock (CP), for clearing the counter to its maximum count and forpresetting the counter either synchronously or asynchronously. In normal operation, thecounter is decremented by one count on each positive-going transition of the clock (CP).Counting is inhibited when the terminal enable input (TE) is HIGH. The terminal countoutput (TC) goes LOW when the count reaches zero if TE is LOW, and remains LOW forone full clock period. When the synchronous preset enable input (PE) is LOW, data at thejam input (P0 to P7) is clocked into the counter on the next positive-going clock transitionregardless of the state of TE. When the asynchronous preset enable input (PL) is LOW,data at the jam input (P0 to P7) is asynchronously forced into the counter regardless ofthe state of PE, TE, or CP. The jam inputs (P0 to P7) represent a single 8-bit binary word.When the master reset input (MR) is LOW, the counter is asynchronously cleared to itsmaximum count (decimal 255) regardless of the state of any other input. If all controlinputs except TE are HIGH at the time of zero count, the counters will jump to themaximum count, giving a counting sequence of 256 clock pulses long. Device may becascaded using the TE input and the TC output, in either a synchronous or ripple mode.Inputs include clamp diodes. This enables the use of current limiting resistors to interfaceinputs to voltages in excess of VCC.

74HC40103D,652 3. Applications

 Divide-by-n counters Programmable timers Interrupt timers Cycle/program counters.