MAX3892ETH+T

MAX3892ETH+T Features

♦ Single +3.3V Supply♦ 455mW Power Consumption♦ 1.4psRMS Maximum Jitter Generation♦ 4 ✕ 4-Bit FIFO Input Buffer♦ 622Mbps/666Mbps Parallel to 2.5Gbps/2.7GbpsSerial Conversion♦ 622MHz/667MHz or 311MHz/333MHz Clock Input♦ On-Chip Clock Synthesizer♦ Multiple Clock Reference Frequencies:(622.08MHz, 155.52MHz, 77.76MHz, 38.88MHz) or(666.51MHz, 166.63MHz, 83.31MHz, 41.66MHz)♦ LVDS Parallel Clock and Data Inputs♦ CML Serial Data and Clock Outputs♦ Additional CML Output for System LoopbackTesting

MAX3892ETH+T General Description

The MAX3892 serializer is ideal for converting 4-bit-wide, 622Mbps parallel data to 2.5Gbps serial data inDWDM and SONET/SDH applications. A 4 ✕ 4-bit FIFOallows for any static delay between the parallel outputclock and parallel input clock. Delay variation up to aunit interval (UI) is allowed after reset. A fully integratedphase-locked loop (PLL) synthesizes an internal2.5GHz serial clock from a 622MHz, 155.5MHz,77.8MHz, or 38.9MHz reference clock. A selectabledual VCO allows excellent jitter performance at bothSONET and forward-error correction (FEC) data rates.Operating from a single 3.3V supply, this deviceaccepts low-voltage differential-signal (LVDS) clock anddata inputs for interfacing with high-speed digital circuit-ry, and delivers current-mode logic (CML) serial dataand clock outputs. A loopback data output is providedto facilitate system diagnostic testing. The MAX3892 isavailable in the extended temperature range (-40°C to+85°C) in 44-pin QFN and TQFN packages.

MAX3892ETH+T Applications