AD8055AR-EBZ

AD8055AR-EBZ FEATURES

Enables quick breadboarding/prototypingUser-defined circuit configurationEdge-mounted SMA connector provisionsEasy connection to test equipment and other circuitsRoHS compliant

AD8055AR-EBZ GENERAL DESCRIPTION

The Analog Devices, Inc., 8-lead SOIC evaluation board isdesigned to help users evaluate single, high speed op ampsoffered in 8-lead SOIC packages. The evaluation board is a bareboard (that is, there are no components or amplifier soldered tothe board, these must be ordered separately) that enables usersto quickly prototype a variety of single op amp circuits, whichminimizes risk and reduces time to market.The evaluation board is a 2-layer printed circuit board (PCB) thataccepts SMA edge-mounted connectors on the inputs and outputsfor efficient connection to test equipment or other circuitry. Theevaluation board is designed to work with almost any of the AnalogDevices op amps offered in an 8-lead SOIC package. The evaluationboard can accommodate amplifiers that feature a power-down ordisable pin. The board can also be used with op amps that featureexternal frequency compensation capacitors, such as the AD8021AR.Figure 1 shows the component side of the bare evaluation board,and Figure 2 shows the circuit side of the bare evaluation board.The ground plane, component placement, and supply bypassinghave been designed to provide maximum flexibility whileminimizing parasitic inductances and capacitances. The componentsof the evaluation board are primarily SMT 1206 case size, withthe exception of the electrolytic bypass capacitors (C1, C4), whichare 3528 case size.Figure 3 shows the evaluation board schematic. The assemblydrawings are shown in Figure 4 and Figure 6. The recommendedlayout patterns for making connections to the op amp andsupporting circuitry are shown in Figure 5 and Figure 7.Two options for supply bypassing include the following:1.Connect additional shunt capacitors (C2, C5) in parallel withthe electrolytic capacitors (C1, C4) from each supply toground. This technique of power supply bypassing provideswideband rejection of unwanted noise on the supply lines. Itis implemented by placing a 0 Ω resistor in the C6 positionand shunt capacitors in the C1, C2, C4, and C5 positions.2.Connect a capacitor between the supply rails. This methoduses fewer components and can improve the PSRR at higherfrequencies but does not provide shunt bypassing to thenegative supply rail. It is implemented by inserting a 0 Ωresistor in the C2 position, then inserting the bypass capacitorin the C5 position, and omitting C6. Optimal bypassing iscircuit dependent and, therefore, must be evaluated by thedesigner for each application.